The present invention relates to a buffer memory control apparatus.
Such a circuit for controlling a buffer memory is disclosed in U.S. Pat. No. 4,332,010 and JP-B-57-57784.
The latest large-sized and medium-sized electronic computers generally employ a virtual storage system as well as a buffer memory system. The virtual storage system is a system in which a programmer can execute coding without being conscious of the size of a real storage by working with a logical address on a virtual storage not a real address on a real storage. On the other hand, the buffer storage system is a system in which a high-speed and small capacity buffer storage is disposed in a main storage so as to stop a speed gap in the main storage. A storage hierarchical structure is thereby formed because the large capacity main storage is low in processing speed in comparison with an operation speed of the computer.
In a virtual storage system, it is necessary to translate a logical address into a real address prior to accessing the main storage. The translation of a logical address into a real address is carried out by making reference to an address translation table prepared in a program. If such reference is made to the low speed main storage every time translation is to be made, the relative overhead time necessary for the translation is great. In this regard, there is provided a translation lookaside buffer (hereinafter abbreviated to "TLB") for storing pairs of logic/address to real address translations which have been obtained by making reference to the main storage, so that when accessing the main storage, a judgment is made whether the logical address in question exists in the TLB or not prior to accessing. If the logical address exists in the TLB (the probability of this existence is very high because of locality of a program), the real address corresponding to the logical address can be obtained at a high speed from the TLB.
In the buffer storage system, on the other hand, the buffer storage is a copy of a part of the main storage and therefore a buffer address array (hereinafter abbreviated to "BAA") is provided in the buffer storage in order to store the correspondency between logical and real addresses. If a central processing unit starts the main storage reference with a logical address, a judgment is made as to whether a real address corresponding to the logical address translated by the TLB exists in the BAA or not so that when the real address exists in the BAA (the probability of this existence is very high because of locality of a program), necessary data is read out from the buffer storage at a high speed and sent to the central processing unit.
Although the above description has been made such that the references to the TLB and BAA are made serially, it is often necessary to make parallel reference to them in order to make the processing speed high. In this case, the BAA is referred to with a logical address. There are however a system in which BAA column identification is made with a real address portion within a logical address or at an intra-page address, and another system in which the identification is made with a logical address or an address including a part of a page address to be subject to address translation. In the latter system, there is an overlapping in bits of the respective identification addresses to be given to the TLB and BAA.
The present invention is applied to the latter system.
FIG. 1 is a block diagram showing a part of a buffer storage device of the system in which reference is made to the above-mentioned TLB and BAA parallelly. Upon generation of a memory request from a central processing unit, a logical address is stored in a register 91. The entry of the logical address in a TLB 92 is identified by a lower bit b of an upper-rank page address of the logical address. In this example, the TLB 92 is composed of k columns .times.2 rows, and the reference numerals 92-1 and 92-2 represent first and second rows respectively. That is, each of the first and second rows has k entries. Each entry in each of the first and second rows 92-1 and 92-2 of the TLB 92 is composed of a logical address portion (L), a validity flag bit portion (V), and a real address portion (R). The logical address portion and real address portion of the TLB are called TLBLA and TLBRA respectively. The contents of the portions L and V read out from each row of the TLB 92 are compared with an upper bit a of the page address in the register 91 by corresponding logical address comparators 94-1 and 94-2 respectively.
The BAA is identified with an upper bit c of a lower rank intra-page address of a virtual address. In this embodiment, the BAA 93 is composed of l columns .times.2 rows and the reference numerals 93-1 and 93-2 represent first and second rows respectively. That is, each row has l entries. Each entry of the BAA 93 is composed of a real address portion (R) and a validity flag bit portion (V). Real address comparators 96-1 and 96-2 compare a real address (intra-page address or displacement) read out from the portion R of the TLB 92-1 and entered through a selector 95 or a real address (intra-page address or displacement) directly stored in the register 91 by the central processing unit with the contents read out from the portion R of the corresponding row 93-1 or 93-2 of the BAA 93. The selector 95 is arranged to select the contents of the register 91 when the central processing unit has stored a real address directly in the register 91, or select the contents of the row 92-1 of the TLB 92 when a logical address has been stored in the register 91. Other comparators 97-1 and 97-2 are arranged to compare the real address read out from the portion R of the row 92-2 of the TLB 92 with the real address read out from the portion R of the corresponding rows 93-1 and 93-2 of the BAA 93. Upon detection of incidence between the two inputs, the output of each of the real address comparators 96-1, 96-2, 97-1 and 97-2 becomes "1".
The results of comparison by the real address comparators 96-1, 96-2, 97-1 and 97-2 are entered into an encoder 98, and after selected, an encoded output (one bit in this example) of the encoder 98 is stored in a upper bit of a register 99. An intra-page address of the register 91 is stored in a lower bit of the register 99. Thus, a buffer storage address corresponding to the logical address or real address stored in the register 91 is obtained. A buffer storage is identified with this address of the register 99 and the data thus read out from the buffer storage is transferred to the central processing unit.
Requiring a high speed property as well as a certain capacity, the TLB 92 and BAA 93 are generally constituted by bipolar memories. FIG. 2 shows a bipolar memory to be used for such a purpose.
In FIG. 2, after decoded in an X-address decoder 110 and a Y-address decoder 114, address signals applied to input pins A.sub.0 -A.sub.2 and A.sub.3 -A.sub.5 of the X- and Y-address decoders 110 and 114 actuate a memory cell 112 through drivers 111 and 113 respectively. In this example, the memory cell 112 is composed of 8.times.8 bits, that is, 64 bits. A selected one bit of the memory cell 112 is led to an output circuit 116 through a sense amplifier 115. The mode becomes a write mode when an input WE (write enable) is valid. In the write mode, an input DI (data-in) is passed through a gate 117 so as to be ANDed with the WE in an AND 118 and another AND 119. Write "1" or Write "0" is made valid by the outputs of the ANDs 118 and 119 so as to give write instructions, through the driver 113, to the bit of the memory cell 112 designated through the address inputs A.sub.0 -A.sub.5.
When used as the aforementioned TLB or BAA, the bipolar memories of the kind as described above are arranged in the form of a matrix to thereby realize a desired word length as well as a desired bit length.
The recent development and improvement of extra high density LSIs has begun to make it possible to realize making electronic computers large in scale and high in processing speed. This tendency will likely be promoted from now on. Thus, logical devices such as operation devices have come to be made of LSIs and to be made high in processing speed. On the other hand, however, the possibility exist that logical portions including bipolar memories may become a critical path which limits a machine cycle in an electronic computer because most parts of the logical portions are occupied by gates which are used to increase addressing to the bipolar memories and to decrease the number of data readings from the bipolar memories, so that it is difficult to constitute the logical portions by LSIs and therefore impossible to make the best use of such LSIs. Further, there is a tendency that a main storage becomes large in its capacity and therefore it is required to make the capacity of a buffer storage large. That is, it is required to increase the BAA capacity. On the other hand, the technique to make bipolar memories highly integrated has been promoted so that it has become possible to realize high speed memories. However, it is not easy to realize a structure of a large capacity BAA by using bipolar memories having such a structure as described above with respect to FIG. 2, because it is required to extremely increase the number of package pins of the bipolar memories.
For example, in the case where a 4K-bit memory is composed of 64 words, each word can accommodate 64 bits, however, about 140 pins are required for address lines, data lines, control lines, and power supply lines, so that the package size of the bipolar memory is limited by the number of those input and output pins.
The above JP-B-57-57784 discloses a device in which a TLB and a BAA are constituted by memories of the type in which comparators are included in an LSI for the BAA. For example, in the JP-B-57-57784, it is intended to solve the above problems by making the portions encircled by broken lines in FIG. 1 be incorporated in a memory chip.
In the above JP-B-57-57784, a real address read out from the TLB is once led to the outside and then entered into the memory chip constituting the BAA so that the real address is compared with a real address read out from the BAA. There is therefore a problem that the number of pins required for input and output of the TLB and BAA increases and propagation delay also increases. There is a further problem that the communication path among the TLB, BAA, comparators provided in a single LSI becomes so long that the signaling time among those elements is prolonged.